How To Write An Assertion Statement

Abstract:

In this case absorption we attack to comment a subset of OVL 2.0 checkers appliance agnate SVA properties. In accomplishing so, we ascertain the adequation amid checkers, or assertions, based on what ascribe sequences they can ascertain as abortion sequences. A alignment appliance a bartering academic apparatus is alive to compute such a accord and is activated to validate the definiteness of the annotation. Experiences and lessons-learned during the abstracts are presented at the end of the paper.

INTRODUCTION

The new Accellera Accessible Assay Library (OVL) [2][3] accepted provides a bell-ringer and accent absolute affirmation library that can be acclimated beyond assorted assay processes; such as acceptable simulation, dynamic-formal, and static-formal assay tools. SystemVerilog Assertions (SVA), allotment of the IEEE Std. 1800-2005 SystemVerilog Accepted [1], is a accepted affirmation accent for allegorical banausic behavior of the architecture and is authentic by abounding EDA vendors’ architecture and assay apparatus flows. OVL is broadly applicative because it is accessible to use and its accessible antecedent cipher allows users to accept the basal semantics back necessary. On the added hand, the adeptness of SVA as a banausic accent enables blunt descriptions of banausic behavior, and absolute affirmation accumulation algorithms accomplish able checker argumentation for use with academic verification. Appropriately it is no abruptness that users accept amid OVL and SVA based on their own adeptness and accomplished experience, rather than the attributes of the languages.

However, because OVL definitions are absolute in accomplishing details, and affidavit through waveforms or accustomed languages yields inaccurate definitions for added circuitous assertions, there exists a ambiguous ambiguity with OVL semantics. Moreover, in adjustment to administer academic assay efficiently, allotment the adapted OVL instantiation appliance altered constant settings is acute against aspersing the complication of a acknowledged appliance of academic tools. Unfortunately, these attenuate characteristics are not able-bodied accepted and are blocked by the basal accomplishing of anniversary OVL assertion.

The addition of this cardboard is to accommodate OVL users with a guideline for appliance OVL in real-world architecture situations by annotating a adumbrative subset of the OVL assertions with its agnate SVA assertions. In accomplishing so, the accomplishing aerial of altered OVL assertions are compared with their analogue SVA descriptions, in agreement of checker argumentation size. We authenticate our after-effects through a alignment that checks the adequation amid OVL and SVA assertions in agreement of their contextual usage; in added words, as ambition assertions, advantage monitors, or assumptions based on academic techniques.

This cardboard contains bristles sections. First, we accommodate an overview of assertions, affirmation languages, and affirmation libraries. Second, we briefly abridge the acceptance of OVL in architecture and verification—namely in acreage assay and advantage monitoring—and the aberration in the requirements of these two applications. Third, OVL is categorized to allegorize the basal accomplishing details, which are mainly through abetting accompaniment apparatus modeling, with or afterwards counters. Fourth, characteristics and relationships amid agnate OVL assertions are discussed, defining adequation and back-up relationships amid assertions with attention to advantage and acreage checking. Their differences are additionally discussed. In the fifth section, the agnate SVA description is exemplified for the OVL assert_window ancestors of assertions, illustrating that SVA can be acclimated as an authentic and blunt blueprint for OVL semantics.

PRELIMINARIES

This area reviews assertions, affirmation libraries, and affirmation languages for use in accouterments verification.

ASSERTION-BASED VERIFICATION

The use of assertions is actual admired in verification. An affirmation is a absolute account of architecture absorbed that allows the award of bugs afterpiece to their source. They are acclimated to fortify interfaces, advance advice amid architecture and assay engineers, accredit bigger advantage measurements, and acquiesce the boilerplate use of academic techniques for anatomic verification.

Assertion-based assay (ABV) is the use of assertions throughout the architecture and assay breeze to advance affection and abbreviate time to market. In agreement of IP, assertions are alike added admired to ensure that apparatus and interfaces are acclimated and reused properly. Assertions are generally acclimated to access architecture aplomb in such areas as interfacing, corner-case behavior, and integration, as able-bodied as ensuring that analytical structures obey their specification.

The ABV alignment attempts to abode the challenges of observability and controllability of a system. The two challenges are algebraic duals. Observability is a admeasurement of how able-bodied centralized states of a arrangement can be accepted by adeptness of its alien outputs. Controllability denotes the adeptness to move a arrangement about aural its absolute agreement amplitude appliance alone assertive acceptable manipulations.

Generally, in assay assertions advice break the observability claiming by accouterment an centralized testing point, but assertions by themselves do not advice with controllability. However, by adopting assertion-based, constraint-driven simulation, or by applying academic acreage blockage techniques to the architecture assertions, we are able to abode the controllability challenge. By including advantage abstracts with the assertions, the assay action provides admired insights by apprehension holes in the ascribe stimuli and anecdotic missing scenarios.

Assertions can be authentic in a array of agency and at altered levels of abstraction. For example, an affirmation can be authentic in a acreage language, through a checker module, or in the anatomy of a directive. Connected affirmation languages, such as SVA and the Acreage Blueprint Accent (PSL) [4], and connected assertions libraries, such as OVL, accept been accessible for a few years.

There are tradeoffs to accede back allotment the blazon of assertions and the alignment to use. It is advantageous to analyze appliance an affirmation accent against an affirmation library basic for coding any authentic assertion. Affirmation languages acquiesce the description of customized properties. The allowances are abstruse and able arrangement analogous and banausic behavior checking. Affirmation languages are generally actual abridged for specific properties. The downsides of appliance an affirmation accent anon are: the accent charge be learned, mistakes in allegorical the backdrop charge be avoided, and circuitous blockage may crave added clay code.

Assertion libraries are pre-verified checker IP. They are bead in solutions for the best accepted checks. Designers may be added adequate appliance checker modules than affirmation languages. There are two downsides of affirmation libraries: if the exact blockage requirements don’t bout the accessible components, the apparatus accept a lot of ambit that charge to be accepted for able application; a checker bore is sometimes not as cellophane as an affirmation language.

Assertion library checkers can be implemented in a array of ways. For example, checkers can be implemented appliance affirmation languages, RTL clay code, or a admixture of both.

Figure 1 illustrates some altered approaches to appliance affirmation checkers.

Figure 1. Assertion/checker methodologies

Figure 1a shows the use of SVA to anon assay architecture signals. Figure 1b shows the use of an affirmation checker that includes SVA cipher internally. Figure 1c shows the use of an affirmation checker which is implemented appliance some clay cipher and SVA. The adjustment of 1a is the best cellophane and can be actual abridged for specific properties. The adjustment of 1c ability be best for actual circuitous checking, such as agreement blockage for PCI Express.

Because of these choices and methodologies it is generally the case that one would appetite to analyze one affirmation to another. This cardboard focuses on this affair in added detail in sections 4 and 5.OVL

The OVL is composed of a set of affirmation checkers that verifies specific backdrop of a architecture (refer to Table 1 for complete account of the 50 OVL checkers). These checkers are instantiated in the architecture to agreement that a authentic action holds true. Anniversary checker includes one or added properties, a advantage measure, a severity control, and advertisement features.

After its acceptance as an Accellera industry accepted in August 2005, the OVL has developed in user adoption. With the contempo absolution of OVL Adaptation 2.0, which supports simulation, academic verification, emulation/acceleration, and synthesis, the OVL is a absolutely open, accumulation methodology.

SVA and SVA Synthesis

SVA is allotment of SystemVerilog [1]. In SVA, banausic backdrop are created in layers. Boolean propositions anatomy the everyman layer. Verilog expressions are acclimated to ascertain the Boolean propositions. Assertive appropriate functions are acclimated frequently to anatomy the propositions: $rose(), $fell(), $stable(), $onehot(), $prev(). These abridge the blueprint of arresting changes, characteristics, and delayed values.

SVA sequences are created from Boolean expressions appliance the SVA arrangement operators. Arrangement operators are agnate to an extended, approved announcement language. SVA has operators for chain and aeon adjournment appliance ## notation, assorted types of arrangement repetition, arrangement or, arrangement and, and the blueprint that a hypothesis be authentic throughout addition sequence.

Properties are authentic appliance SVA sequences. The best accepted forms of backdrop use the able arrangement association operators |-> and |=> to ascertain backdrop from operand sequences.

Finally, assertions, constraints, and advantage credibility are authentic from SVA backdrop in the anatomy of the SVA assay statements assume, assert, and cover.

Table 1. OVL classification

SVA assertions can be apish in activating simulation. SVA can additionally be acclimated to assay architecture backdrop in academic assay [6]. For academic verification, SVA is usually actinic into argumentation that a academic assay apparatus can accomplish on, and the architecture argumentation and the assertions are aggregate into a academic archetypal of the arrangement for verification. SVA assertions can be acclimated in academic as ambition properties; these are the backdrop to check. SVA can additionally be acclimated to ascertain architecture and interface assumptions; these assumptions are additionally alleged constraints.

In this paper, we will bind our focus to assurance acreage checking. Assurance backdrop are assertions that ascertain bad states of the system. Abortion of these backdrop can be presented in the anatomy of a waveform trace from the antecedent accompaniment (typically reset) to the accompaniment area the acreage fails.

The amalgam of an SVA assurance acreage involves the accumulation of the banausic affirmation into an agnate argumentation circuit, which monitors the agnate architecture signals acclimated by the affirmation and detects the abortion states by asserting a abortion arresting that is empiric by the tools.

Generally, to get the best results, performance, and accommodation back appliance academic verification, it is adorable for the academic apparatus to abridge the architecture and affirmation argumentation into as bunched a argumentation representation as possible.

Since affirmation coding styles alter and methodologies to specify assertions alter it is advantageous to accept their complication back actinic and how they analyze in agreement of argumentation size.

Categorizing OVL 2.0

OVL 2.0 contains implementations in four altered languages; namely, Verilog, SVA, PSL, and VHDL. OVL 2.0 has the aboriginal 33 apparatus in Verilog and PSL, 50 (originally 33 additional 17 new) apparatus in SVA, and 10 (a subset of 10 from the aboriginal 33) apparatus in VHDL. For assay and authentic SVA annotation, this cardboard picks up a subset of the aboriginal 33 apparatus from the SVA adaptation of OVL 2.0.

The OVL contains bristles altered classes of assertions; namely, combinatorial, 1-cycle, 2-cycle, N-cycle, and event-bound (refer to Table 1. for complete advertisement of the OVL apparatus and their classes). Because N-cycle and accident apprenticed assertions are the trickiest ones to archetypal in authentic SVA, this cardboard chooses a best of such apparatus for research. The cardboard advocates a alignment for autograph agnate assertions appliance academic verification. Appliance this aforementioned methodology, it additionally presents assay for a dozen OVL components.

The cardboard excludes studies of X/Z blockage and coverage-driven assay that can be done by the OVL 2.0 components. The cold of the abstracts was to apply on the capital assertions in the apparatus that were considered.

Design Decisions abaft OVL Implementation

Keeping the advantage and X/Z blockage implementations aside, the architecture of a specific OVL basic in the SVA adaptation of the library depends aloft the chic of the component.

Being the simplest ones to model, all distinct aeon and combinatorial apparatus are implemented appliance authentic SVA. No abetting clay code—for example, ovl_always and ovl_proposition—was bare or acclimated As such, the library contains alone two combinatorial components: ovl_proposition and ovl_assert_never_unknown_async. No distinct aeon or combinatorial apparatus are called for assay in this paper. All 2-cycle components—for archetype assert_always_on_edge and assert_decrement—are additionally based on authentic SVA implementation. Hence, no such apparatus are called for assay in this paper.

Design of best of the N-cycle and accident apprenticed apparatus in the library uses auxiliary, Verilog clay accompaniment machines and counters. These accompaniment machines and counters—for example, assert_frame, assert_next, assert_win_change, and assert_window—are alive to archetypal windows and advance the counting of delayed cycles over a multi-cycle path. This cardboard annotates these classes of OVL apparatus appliance authentic SVA, thereby alienated use of abetting Verilog accompaniment machines or counters to accomplish the aforementioned functionality.

OVL Implementation

The accomplishing of best of the N-cycle and accident apprenticed assertions in the OVL uses auxiliary, Verilog clay cipher based on counters and accompaniment shifting.

Taking an archetype of an N-cycle OVL component, ovl_change, the accomplishing uses two states, START and CHECK, to encode the accompaniment of the alive component. The accompaniment diagram is apparent in Figure 2.

 

Figure 2. Accompaniment diagram for ovl_change

Auxiliary argumentation is all-important to archetypal functionality that ignores new alpha contest while blockage is already in advance afterwards an beforehand alpha event. The architecture is such that blockage can appear alone aural the accustomed window. The window is modeled per the aloft accompaniment machine. The window opens afterwards the alpha accident is authentic and the accompaniment of the apparatus is START. This accomplishing is activated to apparatus that crave IGNORE_NEW_START functionality. An ERROR-ON-NEW-START functionality accomplishing additionally makes use of this window. However, such functionality can be modeled appliance authentic SVA afterwards the advice of a Verilog accompaniment machine. The abstracts in this cardboard will authenticate this. The OVL components, ovl_unchange, ovl_win_change, ovl_win_unchange, ovl_frame, and ovl_time accept agnate implementations.

OVL components, such as ovl_next, apply decrementing counters to ascertain the window aural which the blockage argumentation of the basic is active. The adverse is acclimated to advance the accepted delayed cycles already a blockage window opens. The overlap assay restricts re-occurrence of alpha accident aural the blockage window, as follows:

start_event |-> calculation <= 1

This agency that a new alpha accident can action alone back the ahead opened window is closing or already closed. However, such functionality can be modeled appliance authentic SVA afterwards the advice of an abetting Verilog adverse that has been modeled separately. The abstracts will authenticate this as well.

The OVL Window Concept

Every OVL affirmation has assorted options that are configurable through parameters. Parameters, such as severity_level, property_type, coverage_level, and msg, are accepted for all apparatus in the OVL. Similarly, function-specific parameters, such as action_on_new_start, are accepted for OVL subset assertions such as assert_frame and assert_change.

These assertions use the abstraction of a window of alive alarm edges aural which the blockage of the analysis expression, test_expr, occurs. The window opens with the affirmation of start_event. It either closes with the affirmation of end_event in some of the checkers or automatically closes afterwards a authentic cardinal of clocks (num_cks) in addition set of checkers. These checkers accept the afterward operating modes:

It is important to agenda that, depending on the blazon of checker, the alarm bend area the window starts or closes is either included aural the window or afar out of the window. If included, the blockage of test_expr would additionally appear on those alarm edges.

In best cases, test_expr blockage is afar at the alarm bend at which a window opens, and the blockage is included at the alarm bend area a window closes. However, this affection varies beyond the window-based ancestors of checkers in the OVL.

For example, in the ovl_unchange checker, by absence the alarm bend at which the window closes is included aural the window. However, back a window is displace aloft the accession of a new start_event (with the OVL_RESET_ON_NEW_START1 advantage enabled), at this alarm edge, the blockage of test_expr is disabled area the old window closes, and a new window opens.

These are the candied spots for annotating the OVL assertions into complete SVA.

Figure 3. Window-based OVL checker implementation

Methodology for Comparing Assertions

To analyze two altered assertions (checkers) that are coded to accomplish a agnate blockage requirement, a alignment for comparing them is required. In this assignment we focus on a alignment for comparing checkers based on the abortion sequences they ascertain over bound traces. For example, in a simulation, one checker may ascertain a abortion that is abandoned by addition implementation.

To analyze assertions formally, a alliance ambit could be created, as is frequently done in adequation checking. This alliance ambit is complete from the actinic accomplishing of the assertions or checkers to be compared. However, generally no such apparatus is accessible because the aggregate abortion signals are not readily accessible for architecture of a alliance circuit.

To accomplish a agnate allegory to a alliance circuit, we alive an assert/assume alignment that is readily authentic by best academic tools. In this assert/assume method, one affirmation is acclimated as the acceptance or coercion for the other, which is set up as the ambition affirmation to be authentic or falsified. Academic assay is performed to assay all accessible affirmation traces. Then, the affirmation and acceptance roles of the two checks are antipodal and the assay is repeated.

In anniversary aeon of the trace, the checker may ascertain a abortion based on the arrangement apparent up to that point. Abstractly, what a authentic checker checks can be visualized as a amplitude that covers all accessible sequences. The failures detected by the checker anatomy a subset of this space. Comparing two checkers is agnate to comparing two abortion subsets.

Consider the altered accessible situations apparent in Figure 4.

Figure 4. Accord amid two assertions

In the aboriginal situation, P1 and P2 both ascertain failures that the added does not. Alone some of the failures are detected by both P1 and P2. Appliance the assert/assume method, both P1 and P2 would be biased back one is the acceptance and the added is the ambition affirmation and carnality versa. In this case, both checkers charge to be advised to actuate if the failures are actual and why there are differences.

In the additional and third situations, one checker finds all the failures of the other, additional more. The assert/assume adjustment proves one assertion, but back the about-face (assert/assume switched) is run, the added affirmation is falsified. These checkers are not the same, as one checks added cases than the other, and these after-effects charge to be inspected to see why.

In the fourth situation, back P1 and P2 are absolutely equivalent, whether the assert/assume alignment runs P1 as an acceptance and P2 as the affirmation or carnality versa, the academic assay will acquisition a affidavit that the assertions are the same. In this case, it is assertive that both implementations are in actuality blockage the aforementioned abortion sequences. However, it is still accessible that both implementations accept a accepted bug if they do not accommodated the advised high-level blockage requirements.

SVA Comment of the assert_window Ancestors of Assertions

Case Study: ovl_frame

In OVL, ovl_frame is one of the window-based checkers. The window is started at start_event and controlled by two parameters: min_cks and max_cks. According to the OVL LRM, the analysis announcement test_expr should not authority in the min_cks of the window, and it should authority at atomic already afore the window closes in max_cks cycles. In the afterward sections, we carbon the checker with altered configurations appliance agnate SVA.

The beginning aftereffect is authentic in the chosen, specific and typical, constant setting. A stronger and accepted affidavit of the agnate for all abuttals altitude is not presented.

ERROR_ON_NEW_START

The aboriginal affair we noticed was that the start_event in this checker is edge-sensitive; in added words, $rose(start_event) is the triggering action for the alpha of the window, and consecutive blockage for NEW_START is additionally based on $rose(start_event).

RESET_ON_NEW_START

The OVL-SVA adaptation of the library seems to accept some problems with this configuration. Instead, we acclimated the OVL-PSL adaptation of the library for the adequation comparison. The afterward shows the agnate SVA affirmation for the OVL-PSL accomplishing of this checker. Agenda that the RESET alone affects the aeon amid min_cks and max_cks, as $rose(start_event) is associated with the after allotment of the LHS sequence.

IGNORE_ON_NEW_START

For this configuration, it turns out to be actual difficult for SVA to model, because the alpha and end of the window around authentic in the OVL checker are actual adamantine to archetypal appliance SVA. On the added hand, a simple Verilog clay state-machine can archetypal this window behavior in a aboveboard way; thus, appliance SVA and the state-machine seems to be the best way to archetypal such a property. Hence, a authentic SVA comment is not complete for this property.

Summary of Results

The complete after-effects are apparent in Figure 5. The third cavalcade shows the after-effects of our experiments, whether the agnate SVA acreage for the agnate OVL checker with a specific constant are acquired or not. For these 12 window-based OVL checkers, agnate SVA descriptions are accessible except for the ones with the agreement of IGNORE_NEW_START.

Figure 5. Comment results

During this process, the OVL semantics are bigger understood, and a few issues accept been begin with the SVA and PSL accomplishing of the checker with attention to its acclimation with the LRM. As there are abounding OVL flavors actuality implemented because of their ease-of-use and accessible affiliation with assorted HDL flavors, a analytical way to validate their definiteness and acclimation with the  LRM turns out to be important to ensure the semantics of the checker itself. The alignment of comparing the adequation amid two assertions provides a accessible way of autograph and debugging the acclimation amid assorted OVL implementations. Issues from this absorption will be submitted to the OVL board for added study.

Conclusion and Future Work

In this case study, we presented our assignment annotating the OVL 2.0 with SVA descriptions in adjustment to actualize a abridged and authentic semantic definition, and we explored a altered alignment for implementing an affirmation library. For an able accomplishing of the broadly acclimated OVL, a alignment of employing affirmation languages as able-bodied as judiciously appliance abetting clay produces the best able implementation. The convenance of appliance SVA to comment OVL checker semantics forth with appliance a academic apparatus for adequation blockage should be activated on any OVL accomplishing with added accent flavors.

ACKNOWLEDGMENT

We would to like acknowledge Todd Burkholder for proofreading and alteration of the aboriginal abstruse and the abstract of this paper.

REFERENCES

[1]     IEEE Std 1800-2005 SystemVerilog Accent Standard, IEEE 2005

[2]     Foster, H., Larsen, K., Turpin, Mike.  Introduction to the new Accellera Accessible Assay Library.  DVCon 2007

[3]     Accellera Accessible Assay Library Standard, Accellera 2007.

[4]     IEEE Std 1850-2005 IEEE Accepted for Acreage Blueprint Accent (PSL).

[5]     Turpin, M.  Timing Diagrams for Accellera Accepted OVL V2.1. September, 2007.

[6]     Long, J., Seawright, A. Synthesizing SVA Local Variables for Academic Verification. IEEE 44th Architecture Automation Conference, San Diego, July 2007.

How To Write An Assertion Statement – How To Write An Assertion Statement
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